High-speed transistors adapted to operate in a microwave band and high-power transistors for use in power conversion are applied to various fields such as household electrical appliances.
As a semiconductor element forming a high-speed transistor or a high-power transistor, there is a bipolar transistor, a thyristor, a GTO, an IGBT, a MOSFET, or the like. Such an element is required to turn on/off the high power at high speed in response to a pulse signal and, thus, for the purpose of satisfying both supply voltage resistance and speediness, use has been made of a semiconductor substrate that differs from an integrated circuit substrate formed in a flat shape.
As the semiconductor substrate that has been used for forming such an element, use has been made, as shown in FIG. 1, of a two-layer structured substrate having a structure in which a low-concentration n-type semiconductor silicon layer 1302 serving as a region for forming an element is stacked on a high-concentration n-type semiconductor silicon layer 1301 serving as a substrate base (or a structure in which the semiconductor conductivity type is reversed, i.e. a low-concentration p-type semiconductor silicon layer is stacked on a high-concentration p-type semiconductor silicon layer). Using an ion implantation technique, an impurity diffusion technique, a lithography technique, and so on, three or four semiconductor silicon layers having different impurity concentrations or different conductivity types are formed on the substrate, thereby forming a desired semiconductor element. In the semiconductor element thus formed, the current flows from the back side to the front side of the substrate (or in the opposite direction). Since the substrate of the element as manufactured has a large thickness of 200 μm to 1 mm, the electrical resistance of the substrate inserted in series in the element is large. Accordingly, using a backside polishing technique to polish the back surface of the high impurity concentration silicon substrate being the support substrate, the substrate thickness of the element is finally reduced to 20 μm to 200 μm for the purpose of reducing the series electrical resistance, and then a metal electrode is provided on the back side, thereby completing the semiconductor element.
The thickness of the semiconductor element finished with the backside polishing is about 200 μm. If the thickness is further reduced, there has arisen a problem that the mechanical strength is reduced to thereby cause breakage of the element, or the like.
In view of this, there has been required a substrate with a thin semiconductor layer, which is free from the problem of element breakage or the like.
As a technique of forming a structure having a thin silicon crystal layer on a metal substrate without using the foregoing backside polishing method, there is a technique, as described in Japanese Patent (JP-B) No. 3191972, which forms a porous silicon layer on a silicon single crystal substrate by an anodization method, then epitaxially grows a silicon single crystal at a temperature of about 950° C. and, after joining it to a metal substrate at a temperature of 800° C., separates the silicon substrate at the porous silicon layer, thereby producing the metal substrate having a thin silicon layer. However, the high temperature of 800° C. or more is used, there has arisen a problem of diffusion of metal atoms into the semiconductor layer and further arisen a problem that it is quite difficult to control an impurity concentration profile when forming the foregoing epitaxial layer in multilayers in advance and thus only the single semiconductor layer or the two-layer stacked semiconductor layers can be obtained, and therefore, the manufacture of a semiconductor element cannot be simplified.
Further, with respect to a plane orientation of a semiconductor silicon crystal for use in a conventional semiconductor element, the interface state density at the silicon/gate insulating film interface is small in a MOSFET or an IGBT and it has been only a {100} plane orientation where a good-quality oxide film with a high withstand voltage is obtained.
With respect to a conventional vertical-type semiconductor element, it has been difficult to form an element having both n-type and p-type polarities in a vertical direction and, in the case of forming a semiconductor circuit such as an inverter, it is formed by mounting individual semiconductor elements on a wiring board.
Referring back to the formation of the semiconductor element, a number of processes such as impurity ion implantation and diffusion are required for forming the semiconductor element and many of them require a thermal process near 1000° C., and therefore, it is difficult to control the impurity distribution in the element and thus the yield is reduced, thereby causing a problem that the element increases in price.
Since only the {100} plane can be used as a substrate plane orientation in terms of manufacturing technology, there has arisen a problem that the diffusion constants of electrons and holes are small and thus it is not possible to increase the speed of current conduction or interruption of the element.
Further, since the element is formed on the silicon substrate, the generated heat of the element is difficult to dissipate to the outside of the element and thus the temperature of the element rises and, therefore, there has arisen a problem that electrons or holes extremely increase, thereby causing thermal malfunction of the element or requiring a complicated temperature compensation circuit.
Further, since it has conventionally been difficult to form a plurality of vertical-type semiconductor elements on a single semiconductor substrate, there has arisen a problem that a semiconductor device formed using these semiconductor elements increases in size.
The foregoing problem that the semiconductor device increases in size due to incapability of integration has caused a problem that wiring connecting the adjacent semiconductor elements increases in distance and thus has caused a problem that the parasitic capacitance and inductance possessed by the wiring increase to disable speed-up of the semiconductor device.